HPCGRA - An Orthogonal Designed CGRA Generator for High Performance Spatial Accelerators - Silva, Lucas; Canesche, Michael; Ferreira, Ricardo; Nacif, José Augusto (Anais do Simpósio em Sistemas Computacionais de Alto Desempenho (SSCAD), 2020)
Recently, the increasing adoption of domain-speciﬁc architectures to execute kernels with high computing density and the exploration of sparse architectures using Systolic Arrays created the ideal scenario for using Coarsegrained reconﬁgurable architectures (CGRAs) to accelerate applications. Unlike Systolic Array, CGRA can run different kernel sets and keep a good balance between energy consumption and performance. In this work, we present the HPCGRA, an orthogonal designed CGRA generator for high-performance spatial accelerators. Our tool does not require any expertise in Verilog design. In our approach, the CGRA is designed and implemented in an orthogonal fashion, through wrapping the main building blocks: functional units, interconnection patterns, routing, and elastic buffer capabilities, conﬁguration words, and memories. It optimizes and simpliﬁes the process of creating CGRAs architectures using a portable description (JSON ﬁle) and generating a generic, scalable, and efﬁcient Verilog RTL code with Veriloggen. The tool automatically generates CGRA with up to 46x66 functional units, reaching 1.2 Tera ops/s.