Introducing Drowsy Technique to Cache Line Usage Predictors - Sokulski, Rodrigo M.; Carreno, Emmanuel D.; Alves, Marco A. Z. (Anais do Simpósio em Sistemas Computacionais de Alto Desempenho (SSCAD); 2018: Anais do XIX Simpósio em Sistemas Computacionais de Alto Desempenho, 2018)
In the last decades, with the continuous increase in the number of transistors on the same chip, a bigger die area inside the processor have been occupied by the cache memories, in some cases, the caches occupy close to half of the chip area in modern processors. For this reason, more energy is consumed by this dedicated circuit, making energy saving techniques for cache memories an important subject. In this paper, we evaluate the integration of a state-of-theart dead cache line predictor with the Drowsy technique to enable static energy savings up to 70% in the last level cache.