Large-Scale RISC-V Processor Verification Using Automated Design Inspection and a Generic Simulation Method - Gomes, Gabriel; Avelar, Julio; Oliveira, Gabriel; Bertoloti, Enzo; Azevedo, Rodolfo (Anais do Simpósio em Sistemas Computacionais de Alto Desempenho (SSCAD); 2025: Anais do XXVI Simpósio em Sistemas Computacionais de Alto Desempenho, 2025)
In recent years, RISC-V ISA has gained popularity and research on RISC-V processor verification has increased. However, most studies focus on a small number of cores and rely on implementation-dependent characteristics. To address this limitation, we propose a generic verification framework that monitors high-level processor states through the fetch interface and the register file write port. The execution traces are compared against a reference model. Our framework leverages a Large Language Model to collect the necessary files and signals of new processors, allowing manual code reductions of 85%. We evaluated the framework by testing 21 LLMs in the inspection task and simulating a custom benchmark on 21 processors, identifying 16 bugs across 8 different cores.