Coherence State Awareness in Way-Replacement Algorithms for Multicore Processors - Souza, Matheus; Freitas, Henrique Cota; Pétrot, Frédéric (Anais do Simpósio em Sistemas Computacionais de Alto Desempenho (SSCAD); 2019: Anais do XX Simpósio em Sistemas Computacionais de Alto DesempenhoDO - 10.5753/wscad.2019.8672, 2019)
Due to their performance impact on program execution, cache replacement policies in set-associative caches have been studied in great depth. Currently, most general-purpose processors are multi-core, and among the very large corpus of research, and much to our surprise, we could not find any replacement policy that does actually take into account information relative to the sharing state of a cache way. Therefore, in this paper we propose to add, as a complement to the classical time-based related way-selection algorithms, an information relative to the sharing state and number of sharers of the ways. We propose several approaches to take this information into account, and our simulations show that LRU-based replacement policies can be slightly improved by them. Also, a much simpler policy, MRU, can be improved by our strategies, presenting up to 3.5× more IPC than baseline, and up to 82% less cache misses.