DrPin: A dynamic binary instumentator for multiple processor architectures
Resumo
Modern applications rely heavily on dynamically loaded shared libraries, making static analysis tools used to debug and understand applications no longer sufficient. As a consequence, dynamic analysis tools are being adopted and integrated into the development and study of modern applications. Building tools that manipulate and instrument binary code at runtime is difficult and error-prone. Because of that, Dynamic Binary Instrumentation (DBI) frameworks have become increasingly popular. Those frameworks provide means of building dynamic binary analysis tools with low effort. Among them, Pin 2 has been by far the most popular and easy to use one. However, since the release of the Linux Kernel 4 series, it became unsupported, and Pin 3 broke backward compatibility. In this work we focus on studying the challenges faced when building a new DBI (DrPin) that seeks to be compatible with Pin 2 API, without the restrictions of Pin 3, that also runs multiple architectures (x86-64, x86, Arm, Aarch64), and on modern Linux systems.Referências
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Mutlu, O. and Moscibroda, T. (2007). Stall-time fair memory access scheduling for chip multiprocessors. In Proceedings of the 40th Annual IEEE/ACM international Symposium on Microarchitecture, pages 146–160. IEEE Computer Society.
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Sanchez, D. and Kozyrakis, C. (2013). Zsim: fast and accurate microarchitectural simulation of thousand-core systems. In ACM SIGARCH Computer Architecture News, volume 41, pages 475–486. ACM.
Seward, J. and Nethercote, N. (2005). Using valgrind to detect undened value errors with bit-precision. In USENIX Annual Technical Conference, General Track, pages 17–30.
Sinnadurai, S., Zhao, Q., and fai Wong, W. (2008). Transparent runtime shadow stack: Protection against malicious return address modications.
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Villa, O., Stephenson, M., Nellans, D., and Keckler, S. W. (2019). Nvbit: A dynamic binary instrumentation framework for nvidia gpus. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, pages 372–383.
Bruening, D., Garnett, T., and Amarasinghe, S. (2003). An infrastructure for adaptive dynamic optimization. In Code Generation and Optimization, 2003. CGO 2003. International Symposium on, pages 265–275. IEEE.
Carlson, T. E., Heirmant, W., and Eeckhout, L. (2011). Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation. In High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for, pages 1–12. IEEE.
Karlsson, B. (2005). Beyond the C++ standard library: an introduction to boost. Pearson Education.
Luk, C.-K., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V. J., and Hazelwood, K. (2005a). Pin: building customized program analysis tools with dynamic instrumentation. In Acm sigplan notices, volume 40, pages 190–200. ACM.
Luk, C.-K., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V. J., and Hazelwood, K. (2005b). Pin: building customized program analysis tools with dynamic instrumentation. In Acm sigplan notices, volume 40, pages 190–200. ACM.
Miller, J. E., Kasture, H., Kurian, G., Gruenwald, C., Beckmann, N., Celio, C., Eastep, J., and Agarwal, A. (2010). Graphite: A distributed parallel simulator for multicores. In High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on, pages 1–12. IEEE.
Mutlu, O. and Moscibroda, T. (2007). Stall-time fair memory access scheduling for chip multiprocessors. In Proceedings of the 40th Annual IEEE/ACM international Symposium on Microarchitecture, pages 146–160. IEEE Computer Society.
Nethercote, N. (2004). Dynamic binary analysis and instrumentation. Technical report, University of Cambridge, Computer Laboratory.
Nethercote, N. and Seward, J. (2007). Valgrind: a framework for heavyweight dynamic binary instrumentation. In ACM Sigplan notices, volume 42, pages 89–100. ACM.
Ravnas, O. A. V. (2016). Frida: A world-class dynamic instrumentation framework.
Sanchez, D. and Kozyrakis, C. (2013). Zsim: fast and accurate microarchitectural simulation of thousand-core systems. In ACM SIGARCH Computer Architecture News, volume 41, pages 475–486. ACM.
Seward, J. and Nethercote, N. (2005). Using valgrind to detect undened value errors with bit-precision. In USENIX Annual Technical Conference, General Track, pages 17–30.
Sinnadurai, S., Zhao, Q., and fai Wong, W. (2008). Transparent runtime shadow stack: Protection against malicious return address modications.
Soares, R., Antonioli, L., Francesquini, E., and Azevedo, R. (2018). Phase detection and analysis among multiple program inputs. In 2018 Symposium on High Performance Computing Systems (WSCAD), pages 155–161. IEEE.
Villa, O., Stephenson, M., Nellans, D., and Keckler, S. W. (2019). Nvbit: A dynamic binary instrumentation framework for nvidia gpus. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, pages 372–383.
Publicado
21/10/2020
Como Citar
ANTONIOLI, Luis Fernando; PANNAIN, Ricardo; AZEVEDO, Rodolfo.
DrPin: A dynamic binary instumentator for multiple processor architectures. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 21. , 2020, Online.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2020
.
p. 251-262.
DOI: https://doi.org/10.5753/wscad.2020.14074.
