Optimizing a Retargetable Compiled Simulator to Achieve Near-Native Performance

Resumo

The design of new architectures can be simplified with the use of retargetable instruction set simulation tools, which can validate the decisions in the design exploration cycle with high flexibility and reduced cost. The increasing system complexity makes the traditional approach to simulation inefficient for today's architectures. The compiled simulation technique makes use of a priori knowledge about the application to accelerate the simulation with high efficiency. This paper presents a retargetable compiled simulator with three optimization techniques and taking advantage of new GCC optimizations to improve the performance. Three architectures were modeled and tested, MIPS, SPARC and PowerPC. Our MIPS model achieved the best results, with average of 651 million instruction per second, and only 2.8 times slower than native execution.