Avaliação de Topologias de Redes-em-Chip usando Simulação de Sistemas Completos e Aplicações Paralelas
Abstract
The Networks-on-Chip approach is an alternative to achieve highperformance computing. In spite of using traditional interconnection systems, this strategy uses routers to enable the communication among the diverse cores in a many-core processor. However, with this approach, the processor performance may be compromised if the interconnection design was not properly planned. The bandwitdh degradation as well as unbalanced loads between the components of the processor could degrade the performance of those architectures. Our work aims to present how the processor performance may be affected by the network-on-chip topology and the design to interconnect memories. The results showed that the cluster topology architectures have better performance than the other architectures.References
Asanovic, K., Bodik, R., Demmel, J., Keaveny, T., Keutzer, K., Kubiatowicz, J., Morgan, N., Patterson, D., Sen, K., Wawrzynek, J., et al. (2009). A view of the parallel computing landscape. Communications of the ACM, 52(10):56–67.
Benini, L. and Micheli, G. D. (2002). Networks on chips: a new soc paradigm. Computer, 35(1):70–78.
Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M. D., and Wood, D. A. (2011). The gem5 simulator. ACM SIGARCH Computer Architecture News, 39(2):1–7.
Butko, A., Garibotti, R., Ost, L., and Sassatelli, G. (2012). Accuracy evaluation of gem5 simulator system. In Recongurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on, pages 1–7. IEEE.
Camacho, J., Flich, J., Duato, J., Eberle, H., and Olesinski, W. (2011). A power-efcient In Proceedings of the Fifth International Workshop on
network on-chip topology. Interconnection Network Architecture: On-Chip, Multi-Chip, pages 23–26. ACM.
Freitas, H. C., Santos, T. G. S., and Navaux, P. O. A. (2008). Design of programmable noc router architecture on fpga for multi-cluster nocs. Electronics Letters, 44(16):969–971.
Freitas, H. C. d., Alves, M. A. Z., and Navaux, P. O. A. (2009). Noc e nuca: Conceitos e tendências para arquiteturas de processadores many core. In IX Escola Regional de Alto Desempenho (ERAD), pages 364–366, Caxias do Sul. SBC.
Gutierrez, A., Pusdesris, J., Dreslinski, R. G., Mudge, T., Sudanthi, C., Emmons, C. D., In Hayenga, M., and Paver, N. (2014). Sources of error in full-system simulation. Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on, pages 13–22. IEEE.
Ho, R., Mai, K. W., and Horowitz, M. A. (2001). The future of wires. Proceedings of the IEEE, 89(4):490–504.
Shalf, J., Dosanjh, S., and Morrison, J. (2010). Exascale computing technology challenges. In High Performance Computing for Computational Science (VECPAR), pages 1–25. Springer, Berkeley, USA.
Simon, H. (2012). Barriers to exascale computing. In High Performance Computing for Computational Science (VECPAR), pages 1–3. Springer, Kope, Japan.
Souza, M. A. (2015). Exploração de espaço de projeto de arquiteturas de processadores many-core baseados em redes-em-chip com uso de simulação de sistemas completos. Master's thesis, Pontifícia Univarsidade Católica de Minas Gerais, Brazil.
Souza, M. A., Penna, P. H., Queiroz, M. M., Pereira, A. D., Góes, L. F. W., Freitas, H. C., Castro, M., Navaux, P. O., and Méhaut, J.-F. (2016). Cap bench: a benchmark suite for performance and energy evaluation of low-power many-core processors. Concurrency and Computation: Practice and Experience, pages n/a–n/a. cpe.3892.
Udipi, A. N., Muralimanohar, N., and Balasubramonian, R. (2010). Towards scalable, energy-efcient, bus-based on-chip networks. In HPCA-16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, pages 1–12, Bangalore. IEEE, IEEE.
Wang, R., Chen, L., and Pinkston, T. M. (2013). An analytical performance model for partitioning off-chip memory bandwidth. In Parallel & Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on, pages 165–176. IEEE.
Xu, T. C., Schley, G., Liljeberg, P., Radetzki, M., Plosila, J., and Tenhunen, H. (2013). Optimal placement of vertical connections in 3d network-on-chip. Journal of Systems Architecture, 59(7):441–454.
Benini, L. and Micheli, G. D. (2002). Networks on chips: a new soc paradigm. Computer, 35(1):70–78.
Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M. D., and Wood, D. A. (2011). The gem5 simulator. ACM SIGARCH Computer Architecture News, 39(2):1–7.
Butko, A., Garibotti, R., Ost, L., and Sassatelli, G. (2012). Accuracy evaluation of gem5 simulator system. In Recongurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on, pages 1–7. IEEE.
Camacho, J., Flich, J., Duato, J., Eberle, H., and Olesinski, W. (2011). A power-efcient In Proceedings of the Fifth International Workshop on
network on-chip topology. Interconnection Network Architecture: On-Chip, Multi-Chip, pages 23–26. ACM.
Freitas, H. C., Santos, T. G. S., and Navaux, P. O. A. (2008). Design of programmable noc router architecture on fpga for multi-cluster nocs. Electronics Letters, 44(16):969–971.
Freitas, H. C. d., Alves, M. A. Z., and Navaux, P. O. A. (2009). Noc e nuca: Conceitos e tendências para arquiteturas de processadores many core. In IX Escola Regional de Alto Desempenho (ERAD), pages 364–366, Caxias do Sul. SBC.
Gutierrez, A., Pusdesris, J., Dreslinski, R. G., Mudge, T., Sudanthi, C., Emmons, C. D., In Hayenga, M., and Paver, N. (2014). Sources of error in full-system simulation. Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on, pages 13–22. IEEE.
Ho, R., Mai, K. W., and Horowitz, M. A. (2001). The future of wires. Proceedings of the IEEE, 89(4):490–504.
Shalf, J., Dosanjh, S., and Morrison, J. (2010). Exascale computing technology challenges. In High Performance Computing for Computational Science (VECPAR), pages 1–25. Springer, Berkeley, USA.
Simon, H. (2012). Barriers to exascale computing. In High Performance Computing for Computational Science (VECPAR), pages 1–3. Springer, Kope, Japan.
Souza, M. A. (2015). Exploração de espaço de projeto de arquiteturas de processadores many-core baseados em redes-em-chip com uso de simulação de sistemas completos. Master's thesis, Pontifícia Univarsidade Católica de Minas Gerais, Brazil.
Souza, M. A., Penna, P. H., Queiroz, M. M., Pereira, A. D., Góes, L. F. W., Freitas, H. C., Castro, M., Navaux, P. O., and Méhaut, J.-F. (2016). Cap bench: a benchmark suite for performance and energy evaluation of low-power many-core processors. Concurrency and Computation: Practice and Experience, pages n/a–n/a. cpe.3892.
Udipi, A. N., Muralimanohar, N., and Balasubramonian, R. (2010). Towards scalable, energy-efcient, bus-based on-chip networks. In HPCA-16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, pages 1–12, Bangalore. IEEE, IEEE.
Wang, R., Chen, L., and Pinkston, T. M. (2013). An analytical performance model for partitioning off-chip memory bandwidth. In Parallel & Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on, pages 165–176. IEEE.
Xu, T. C., Schley, G., Liljeberg, P., Radetzki, M., Plosila, J., and Tenhunen, H. (2013). Optimal placement of vertical connections in 3d network-on-chip. Journal of Systems Architecture, 59(7):441–454.
Published
2016-10-05
How to Cite
CARMO, Daniel; SOUZA, Matheus; FREITAS, Henrique.
Avaliação de Topologias de Redes-em-Chip usando Simulação de Sistemas Completos e Aplicações Paralelas. In: SYMPOSIUM ON HIGH PERFORMANCE COMPUTING SYSTEMS (SSCAD), 17. , 2016, Aracajú.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2016
.
p. 109-120.
DOI: https://doi.org/10.5753/wscad.2016.14252.
