Como executar sua simulação em múltiplos processadores sem modificar nem seus módulos nem o SystemC

Tiago Falcão; Liana Duenha; Rodolfo de Azevedo

doi:10.5753/wscad.2015.14274

Tiago Falcão UNICAMP
Liana Duenha UFMS
Rodolfo de Azevedo UNICAMP

DOI: https://doi.org/10.5753/wscad.2015.14274

Abstract

Simulation is one of the main stages in the validation process in systems design; in this stage, system architects can verify the correctness, behavior, and performance of the target system. SystemC is a System-level Description Language (SLDL), a C++ language extension that supports different abstraction levels. The downside is its sequential simulation model that does not take advantage of the parallel processing capabilities. This paper proposes a generic technique that allows the simulation of a set of SystemC components by encapsulating each one in a process, which can be scheduled over cores or distributed on a cluster. The main advantage of this approach is that it parallelize SystemC-TLM2 simulators using the original SystemC Kernel and models.

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