Avaliando DTM em Arquiteturas Superescalares Configuradas com Diferentes Larguras

Amarildo T. da Costa; Felipe M. G. França; Eliseu M. C. Filho

doi:10.5753/wscad.2001.19124

Amarildo T. da Costa IME / UFRJ
Felipe M. G. França UFRJ
Eliseu M. C. Filho UFRJ

DOI: https://doi.org/10.5753/wscad.2001.19124

Abstract

This work evaluates the exploration of redundancy at the trace level (sequences of dynamic instructions) applied to superscalar processors with different widths. The existing redundancy in programs was explored through a reuse mechanism called Dynamic Trace Memoization (DTM). Simulations considering processors configured with different widths and incorporating the DTM mechanism, had identified for the SPEC95 benchmarks: reuse percents from 28% to 60% (harmonic mean); speedup percents from 6.3% to 25% (harmonic mean); and that a superscalar processor with width 4 and incorporating the DTM mechanism, outperform in performance the same base superscalar processor with width 8. This last result supplies strong indications of that the redundancy exploration at the trace level is a viable alternative to the option of magnifying the widths of superscalar processors to increase the number of executed instructions per clock cycle.

Keywords: Trace Reuse, Memoization, lnstruction Reuse, Superscalar Processor

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