Large-Scale RISC-V Processor Verification Using Automated Design Inspection and a Generic Simulation Method
Abstract
In recent years, RISC-V ISA has gained popularity and research on RISC-V processor verification has increased. However, most studies focus on a small number of cores and rely on implementation-dependent characteristics. To address this limitation, we propose a generic verification framework that monitors high-level processor states through the fetch interface and the register file write port. The execution traces are compared against a reference model. Our framework leverages a Large Language Model to collect the necessary files and signals of new processors, allowing manual code reductions of 85%. We evaluated the framework by testing 21 LLMs in the inspection task and simulating a custom benchmark on 21 processors, identifying 16 bugs across 8 different cores.References
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Bruns et al. (2023). Processor verification using symbolic execution: A risc-v case-study. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1–6.
Choudhary, N. K. et al. (2011). Fabscalar: Composing synthesizable rtl designs of arbitrary cores within a canonical superscalar template. In 2011 38th Annual International Symposium on Computer Architecture (ISCA), pages 11–22.
Cui et al. (2023). A hardware-software cooperative interval-replaying for fpga-based architecture evaluation. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1–2. IEEE.
Herdt, V., Große, D., Jentzsch, E., and Drechsler, R. (2020). Efficient cross-level testing for processor verification: A risc-v case-study. In 2020 Forum for Specification and Design Languages (FDL), pages 1–7.
Jiang, Z., Zheng, K., Bao, Y., and Shi, K. (2024). Efficient verification framework for risc-v instruction extensions with fpga acceleration. In 2024 2nd International Symposium of Electronics Design Automation (ISEDA), pages 345–350. IEEE.
Joannou, A. et al. (2024). Randomized testing of risc-v cpus using direct instruction injection. IEEE Design & Test, 41(1):40–49.
Kabylkas, N., Thorn, T., Srinath, S., Xekalakis, P., and Renau, J. (2021). Effective processor verification with logic fuzzer enhanced co-simulation. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, pages 667–678.
Liu, S. et al. (2025). Rtlcoder: Fully open-source and efficient llm-assisted rtl code generation technique. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 44(4):1448–1461.
Lozhkov, A., Li, R., Allal, L. B., Cassano, F., et al. (2024). Starcoder 2 and the stack v2: The next generation.
Nijkamp, E. et al. (2023). Codegen: An open large language model for code with multiturn program synthesis.
OpenCores (2010). Wishbone system-on-chip (soc)interconnection architecture for portable ip cores. [link]. [Online; accessed 26-August-2025].
Orenes-Vera, M., Manocha, A., Wentzlaff, D., and Martonosi, M. (2021). Autosva: democratizing formal verification of rtl module interactions. In 2021 58th ACM/IEEE Design Automation Conference (DAC), pages 535–540. IEEE.
RISC-V Foundation (2025). RISC-V Certification Steering Committee. [link]. [Online; accessed 26-August-2025].
Rokicki, S., Pala, D., Paturel, J., and Sentieys, O. (2019). What you simulate is what you synthesize: Designing a processor core from c++ specifications. In 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1–8.
Schubert, K.-D. et al. (2018). Addressing verification challenges of heterogeneous systems based on ibm power9. IBM Journal of Research and Development, 62(4/5):11:1–11:12.
Synopsys (2025). ImperasDV RISC-V Processor Verification Solution. [link]. [Online; accessed 26-August-2025].
Takamaeda-Yamazaki, S. (2015). Pyverilog: A python-based hardware design processing toolkit for verilog hdl. In Sano, K., Soudris, D., Hübner, M., and Diniz, P. C., editors, Applied Reconfigurable Computing, pages 451–460, Cham. Springer International Publishing.
Thakur, S. et al. (2023). Benchmarking large language models for automated verilog rtl code generation. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1–6.
The FOSSi Foundation (2025). Cocotb python verification framework. [link]. [Online; accessed 26-August-2025].
Wang, J., Tan, N., Zhou, Y., Li, T., and Xia, J. (2020). A uvm verification platform for risc-v soc from module to system level. In 2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM), pages 242–246. IEEE.
Weingarten, L., Datta, K., Kole, A., and Drechsler, R. (2024). Complete and efficient verification for a risc-v processor using formal verification. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1–6.
Xu, Y. et al. (2022). Towards developing high performance risc-v processors using agile methodology. In 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 1178–1199. IEEE.
Yosys (2025). RISC-V Formal Verification Framework. [link]. [Online; accessed 26-August-2025].
Published
2025-10-28
How to Cite
GOMES, Gabriel; AVELAR, Julio; OLIVEIRA, Gabriel; BERTOLOTI, Enzo; AZEVEDO, Rodolfo.
Large-Scale RISC-V Processor Verification Using Automated Design Inspection and a Generic Simulation Method. In: SYMPOSIUM ON HIGH PERFORMANCE COMPUTING SYSTEMS (SSCAD), 26. , 2025, Bonito/MS.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2025
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p. 181-192.
DOI: https://doi.org/10.5753/sscad.2025.16339.
